Instruction Hazards in Pipelining - Tutorials Hub

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15 June 2020

Instruction Hazards in Pipelining

Instruction Hazards in Pipelining

The hazard or conflict that arises due to the alteration caused in the corresponding execution timing of the overlapped nations because of pipelining is called instruction or control hazards.

These hazards primarily arise due to conditional instructions (such as, jump) that alter the flow of instruction, resulting in change in the contents of Program Counter (PC). Because of this change in PC value, the number of instructions to be fetched not certain and hence unnecessary instructions are fetched requiring them to be flushed.

 Furthermore, other problems with instruction hazards and their corresponding avoiding techniques are as follows

1. Branch penalty
2. Delayed branching
3. Conditional branching

Branch Penalty
 The following are the two factors which results in penalty of branches.

a) Instruction Set

Computers utilizing complex instruction set incur much penalties for branches than RISC based systems.

b) Depth of Pipeline 

Implementing pipeline to a large extent also increases the risk of branch penalties.

Avoiding Measures 
An effective way of decreasing branch penalties is through compiler scheduling methods that avoid it by occupying the "delay slot" with some useful instruction

2.  Delayed Branching

The methods that are utilized to fill the delay slot are called delayed branching and these are of three types.

(a) Independent Instruction Delayed Branching

This is a performance enhancing method wherein the delay slot is occupied by an independent instruction prior to the branch.

(b) Target Branch Instruction Delayed Branching 

This method occupies the slot by filling it from target branch instruction and performance enhancement depends on the selection of branch. That is, it is possible only if branch is taken.

(c) Fall Through Instruction Delayed Branching

This method occupies the delay slot by filling it with a fall through instruction and performance enhancement is possible if the branch is ignored or not taken

3. Conditional Branching 
   The performance of instruction pipelining greatly depends on conditional branching.

Avoiding Measures 
The different measures that can help in managing conditional branches are as follows,

(a) Multiple Streams

This techniques utilizes multiple streams to avoid penalty of branch instruction. Here, two streams store the fetched in struction, on stores instructions after the conditional branch and others stores the instruction from the branch address.

(b) Prefetch Branch Target

This technique avoids conditional branching by prefetching the branch target on determining a condition.

(c) Loop Buffer

This technique avoids conditional branching by utilizing a small high speed memory, which stores recently prefetched instructions in order.

(d) Branch Prediction

This techniques avoids conditional branching by analyzing whether a branch will be valid or invalid. The different branch prediction methods are as follows,

(i) Predict never taken

(ii) Predict always taken

(iii) Predict by opcode

(iv) Taken not taken switch

(v) Branch history table.

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